{"id":23,"date":"2026-04-02T22:31:34","date_gmt":"2026-04-02T22:31:34","guid":{"rendered":"https:\/\/llama.gs\/blog\/?p=23"},"modified":"2026-04-02T22:31:34","modified_gmt":"2026-04-02T22:31:34","slug":"from-dsl-to-fpga-closing-the-loop","status":"publish","type":"post","link":"https:\/\/llama.gs\/blog\/index.php\/2026\/04\/02\/from-dsl-to-fpga-closing-the-loop\/","title":{"rendered":"From DSL to FPGA: Closing the Loop"},"content":{"rendered":"

This quarter, 4,500 CEOs told PwC<\/a> their AI investments produced nothing. Separately, someone used AI to rewrite SQLite in Rust<\/a> \u2014 2,000 times slower. I have a cunning plan: what if we used computers to do actual computing?<\/p>\n

Last week I said I was building a toolchain that goes from formal logic to real hardware. That post was a manifesto. This one is a receipt.<\/p>\n

Seven days later: a full ALU \u2014 add, subtract, multiply, divide, integer factorization \u2014 running at 100MHz on a $150 Basys3 FPGA<\/a>. UART command line with tab completion and history. No manual Verilog. No hand-optimized netlists. No venture capital. No pitch deck.<\/p>\n

The arithmetic circuits are generated programmatically in llogic<\/a>, translated to synthesizable Verilog by llogic2verilog<\/a>, and deployed on a MicroBlaze soft processor over AXI4-Lite. The entire path from logical specification to working silicon is automated. One person, one week, open source.<\/p>\n

https:\/\/llama.gs\/blog\/wp-content\/uploads\/2026\/04\/llogic_basys3.mp4<\/a><\/video><\/div>\n

The factor<\/code> command brute-forces integer factorization by driving the multiplier at clock speed \u2014 100 million candidates per second on a hobby board. Not a simulation. Not a testbench. Electrons moving through gates on a Xilinx Artix-7.<\/p>\n

Nobody wrote this Verilog<\/h2>\n

That’s the point. Not the ALU \u2014 any undergraduate can write an adder. The point is that no human touched the HDL.<\/p>\n

The circuit specifications live in llogic<\/a>‘s DSL \u2014 a formal representation that spans Boolean formulas, CNF, circuits, and reversible\/quantum circuits under one roof. lcfgen<\/a> generates parameterized circuit families from that representation. llogic2verilog<\/a> translates them to synthesizable Verilog. Vivado takes it the rest of the way.<\/p>\n

llogic<\/a> DSL \u2192 lcfgen<\/a> \u2192 llogic2verilog<\/a> \u2192 Vivado \u2192 FPGA<\/a><\/strong><\/p>\n

Every step automated. Every component open source. No license fees, no NDAs, no EDA vendor lock-in.<\/p>\n

What’s next<\/h2>\n

If you work on synthesis, hardware, or you’re funding research \u2014 the code is open and the board costs $150.<\/p>\n

Next post: cryptographic circuit generators for DES and SHA, synthesized from the DSL, deployed to the FPGA. After that: an open-source architecture for SHA-1 collision hunting that makes Bitcoin’s address space look rather less comfortable. All designs public \u2014 because if the vulnerability exists, pretending otherwise is just poor manners. Any coins found can fund something useful. Clean energy. Quantum computing. Not espresso machines with a subscription model<\/a>.<\/p>\n

Ceterum censeo slopem esse delendam.<\/em><\/p>\n

(Cato the Elder ended every speech in the Roman Senate with “Carthage must be destroyed” \u2014 regardless of the topic. This is that, but for AI slop.)<\/p>\n

Repositories:<\/strong><\/p>\n